1. Field of the Invention
The present invention relates to an analog-to-digital converter and more particularly to a series-parallel A-D converter.
2. Description of the Background Art
FIG. 15 is a diagram of a conventional series-parallel A-D converter disclosed by Andrew G. F. Dingwall in "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE Journal of Solid States Circuits, vol. SC-20, NO. 6, pp. 1138-1143, December 1985. For the purpose of simplication, high-order (coarse) resolution of the A-D converter is three bits long, low-order (fine) resolution thereof is three bits long, and redundancy for error correction is one bit long. Referring to FIG. 15, a reference potential generating circuit 1 outputs high-order reference potentials for 3-bit high-order conversion to high-order reference potential output lines CR0 to CR6 and outputs low-order reference potentials for 4-bit low-order conversion (including the error correction bit) to analog bus lines FR0 to FR14 as a function of high and low potential references VRT and VRB applied respectively to terminals 2 and 3 and a control signal 32 inputted to a signal line 4.
High-order voltage comparators CC0 to CC6 compare the potential of an analog signal to be converted (hereinafter referred to as a "sample signal") which is inputted to a terminal 5 with the high-order reference potentials to give the result to a high-order encoder 6. The high-order encoder 6 gives the control signal 32 and a 3-bit high-order A-D conversion result 33 to the signal line 4 and an error correction circuit 7, respectively.
Low-order voltage comparators FC0 to FC14 compare the sample signal potential with the low-order reference potentials to give the result to a low-order encoder 8. The low-order encoder 8 gives a 3-bit low-order A-D conversion result to a terminal 9 and gives an error detection signal 34 to the error correction circuit 7 through a signal line 10, respectively.
The error correction circuit 7 corrects errors of the high-order A-D conversion result 33 as a function of the error detection signal 34 to give a corrected 3-bit high-order A-D conversion result 35 to a terminal 11.
A structure of the reference potential generating circuit 1 to be used for the series-parallel A-D converter is shown in FIG. 16. The reference potential generating circuit 1 used for 6-bit A-D conversion includes 2.sup.6 resistors r connected in series between the terminals 2 and 3 and having the same resistance to form a ladder resistor. The ladder resistor is divided into 2.sup.3 resistor groups R0 to R7 each including 2.sup.3 adjacent resistors connected in series. The connecting points of the eight resistor groups R0 to R7 are connected to the high-order voltage comparators CC0 to CC6 through the high-order reference potential output lines CR0 to CR6. The high-order reference potential output lines CR0 to CR6 are connected to the connecting points CRl (1=0 to 7) of the resistor groups Rl and R(l+1). Potentials VCl at the connecting points CRl, the potentials VRT, VRB at the terminals 2, 3 and divided potentials V(l,m) (l=0 to 7, m=0 to 6) in the resistor groups R0 to R7 serve as the reference potentials and are inputted to a switch matrix 12. Fifteen potentials having adjacent levels among the reference potentials are applied to the analog bus lines FR0 to FR14 by the control to be described later to be inputted to the voltage comparators FC0 to FC14 as the low-order reference potentials.
An arrangement of the switch matrix 12 is shown in FIG. 17. The horizontal lines of FIG. 17 represent potential lines connected to the points connecting the 2.sup.6 resistors and to the terminals 2, 3, and potentials of 65 levels are applied to the potential lines. The higher potentials of the 65 levels are applied to the upper lines of FIG. 17. The potentials of 65 levels are classified into eight voltage zones Z0 to Z7. That is, the voltage zone Z0 includes the low-order reference potentials satisfying: EQU VRB&lt;V(0,i)&lt;V(0,i+1)&lt;VC0 (i=0, 1, . . . , 5) (1).
The voltage zones Zj (j=1, 2, . . . , 6) include the low-order reference potentials satisfying: EQU VC(j-1)&lt;V(j,i)&lt;V(j,i+1)&lt;VCj (i=0, 1, . . . , 5) (2).
The voltage zone Z7 includes the low-order reference potentials satisfying: EQU VC6&lt;V(7,i)&lt;V(7,i+1)&lt;VRT (i=0, 1, . . . , 5) (3).
The potentials VCj thus belong to both the zones Zj and Z(j+1). Relation between the potential lines to which the potentials V(j, i) are applied and the zones Zj is shown in detail in FIG. 18 where VC(j-1) when j=1 indicates VRB and VCj when j=6 indicates VRT.
The vertical lines of FIG. 17 represent the analog bus lines FR0 to FR14 to which fifteen out of 65 levels of potentials are applied by switch groups to be classified in the manner as described below. The application is performed by eight switch groups which perform different operations depending on the result of the high-order A-D conversion provided by the control signal 32 of FIG. 15. The switch groups indicated by [0], [1], [2], [3], [4], [5], [6], [7] turn on when the potential of the sample signal falls in the voltage zones Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7 as a result of the high-order A-D conversion, respectively.
The series-parallel A-D converter operates in two stages. In the first stage, the sample signal potential is compared with the high-order reference potentials applied to the high-order reference potential output lines CR0 to CR6 in the high-order voltage comparators CC0 to CC6 (FIG. 15), respectively. The comparison result is converted to the high-order A-D conversion result 33 composed of 3-bit binary codes through the high-order encoder 6.
In the second stage, the control signal 32 outputted from the high-order encoder 6 is inputted to the reference potential generating circuit 1 through the signal line 4. If the sample signal potential falls, for example, in the voltage zone Z3 as a result of the high-order A-D conversion, only the switches indicated by [3] should be turned on. However, contradictions are sometimes caused between the high-order and low-order A-D conversion results. The low-order reference potentials are determined in the voltage zones including and wider than the voltage zone Z3 so that the error correction is enabled to be made against the contradictions in the error correction circuit 7. In this example, an allowance of .+-.4LSB is added to the voltage zone Z3 to determine the low-order reference potentials. Since the high-order reference potential VC3 belongs to both the voltage zones Z3 and Z4, the bus line FR11 connected through the switches disposed therein is counted twice. The LSB is a voltage corresponding to one bit of the A-D converter and is equal to a potential difference across the resistor r in this case. The switches also turn on which are indicated by [3] and disposed on the four bus lines FR11 to FR14 (corresponding to potentials higher than the maximum of the voltage zone Z3) and the four bus lines FR0 to FR3 (corresponding to potentials lower than the minimum of the voltage zone Z3).
The operating speed of the series-parallel A-D converter largely depends on a settling time of the low-order reference potentials outputted from the reference potential generating circuit 1 to the analog bus lines FR0 to FR14. Since the low-order reference potentials are applied to the low-order voltage comparators FC0 to FC14 through the analog bus lines FR0 to FR14 having a large parasitic capacitance, the settling time thereof prevents the high-speed operation of the A-D converter. In the conventional A-D converter for totaling six bits composed of three bits for high-order conversion and three bits for low-order conversion, if 1-bit high-order redundancy is provided, the number of analog bus lines is: EQU (2.sup.3 -1)+2.sup.3 =15 (4)
The number of switches per bus line is at least eight (respective one switch indicated by [0], [1], [2], [3], [4], [5], [6], [7]). Letting the parasitic capacitance of the switches and wires per analog bus line be 1 pF, the total capacitance of fifteen analog bus lines is 15 pF. This means that the capacitance of 15 pF is added to each section of the ladder resistor corresponding to the respective eight voltage zones in accordance with the high-order A-D conversion result. This capacitance exponentially increases as the number of switches increases with the increase in the number of bits of the A-D conversion.
This causes the level of the low-order reference potentials to vary largely transiently when the switches are opened and closed, so that it takes time to settle the level on the original level. The settling time is shortened by reducing the impedance of the ladder resistor. However, for reduction in the impedance of the resistor, it is necessary to increase the cross-sectional area thereof, resulting in a large layout area unpreferably. The analog bus lines accordingly need long wires, accompanied by large wiring capacitance. Thus such attempt is not so effective.
Another factor that prolongs the settling time of the low-order reference potentials is large variation in sample signal level. Which one of the eight resistor groups R0 to R7 outputs the low-order reference potentials depends on the sample signal level. In extreme case, the switches indicated by [7] turn on in response to a first sample signal and the switches indicated by [0] turn on in response to the next sample signal. In this case, the potentials in the voltage zone Z7 nearest to the terminal 2 which have the highest level among the eight voltage zones are applied to the analog bus lines FR0 to FR14 in response to the first sample signal. The potentials in the voltage zone Z0 nearest to the terminal 3 which have the lowest level are applied thereto in response to the next sample signal. Since the potential difference between the terminals 2 and 3 is equal to the maximum amplitude of the sample signal detected by the A-D converter, a potential variation approximate to the maximum amplitude takes place in response to the sample signals in the analog bus lines FR0 to FR14 under the foregoing conditions. This is not so significant a problem since the analog bus lines FR0 to FR14 are connected to the connecting points of the resistors adjacent the terminals 2, 3 having the low impedance in response to the two sample signals. However, the settling time of the low-order reference potentials grows long when the potential variation of the analog bus lines FR0 to FR14 is large and the second sample signal potential falls in the voltage zone having a large impedance of the ladder resistor, e.g., in such a case that the switches indicated by [7] or [0] turn on in response to the first sample signal and the switches indicated by [3] or [4] turn on in response to the second sample signal.
As above described, since the analog bus lines have the large parasitic capacitance and, in particular, the low-order reference potentials to be applied to the analog bus lines largely vary in accordance with the sample signal level, the conventional series-parallel A-D converter is disadvantageous in that the low-order reference potentials outputted from the reference potential generating circuit take a long settling time which prevents the high-speed operation thereof.